Messages in this thread | | | Date | Mon, 11 Sep 2023 10:38:56 +0800 | From | Yu-Chien Peter Lin <> | Subject | Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata |
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Hi Samuel,
On Wed, Sep 06, 2023 at 09:48:35PM -0500, Samuel Holland wrote: > If the code here needs to be different, then it must check that it is actually > running on an Andes core, not just that the errata Kconfig option is enabled.
Thank you for catching this, will fix in PATCH v2.
> However, I suggest setting riscv_pmu_irq_num to the real IRQ number: > riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU; > and then adding a new variable for the mask: > riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG); > which handles the large IRQ number somewhat more generically, and reduces the > number of bit operations needed elsewhere in the driver.
I will make changes according to your suggestions. Thank you!
> Or we could use IRQ chip operations here instead of direct CSR acccess. But > maybe the direct CSR access is needed for performance? > > Regards, > Samuel
Best regards, Peter Lin
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