Messages in this thread | | | Date | Fri, 4 Aug 2023 10:51:46 -0300 | From | Jason Gunthorpe <> | Subject | Re: [PATCH v12 2/8] iommu: Move global PASID allocation from SVA to core |
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On Wed, Aug 02, 2023 at 02:24:21PM -0700, Jacob Pan wrote: > Intel ENQCMD requires a single PASID to be shared between multiple > devices, as the PASID is stored in a single MSR register per-process > and userspace can use only that one PASID. > > This means that the PASID allocation for any ENQCMD using device driver > must always come from a shared global pool, regardless of what kind of > domain the PASID will be used with. > > Split the code for the global PASID allocator into > iommu_alloc/free_global_pasid() so that drivers can attach non-SVA > domains to PASIDs as well. > > This patch moves global PASID allocation APIs from SVA to IOMMU APIs. > Reserved PASIDs, currently only RID_PASID, are excluded from the global > PASID allocation. > > It is expected that device drivers will use the allocated PASIDs to > attach to appropriate IOMMU domains for use. > > Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> > Reviewed-by: Kevin Tian <kevin.tian@intel.com> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> > --- > v8: fix off-by-one in max_pasid check > v7: simplify range check (Baolu) > v6: explicitly exclude reserved a range from SVA PASID allocation > check mm PASID compatibility with device > v5: move PASID range check inside API so that device drivers only pass > in struct device* (Kevin) > v4: move dummy functions outside ifdef CONFIG_IOMMU_SVA (Baolu) > --- > drivers/iommu/iommu-sva.c | 29 ++++++++++------------------- > drivers/iommu/iommu.c | 28 ++++++++++++++++++++++++++++ > include/linux/iommu.h | 10 ++++++++++ > 3 files changed, 48 insertions(+), 19 deletions(-)
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Jason
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