Messages in this thread | | | Date | Fri, 4 Aug 2023 16:28:52 +0800 | From | Chao Gao <> | Subject | Re: [PATCH v5 11/19] KVM:VMX: Emulate read and write to CET MSRs |
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>+ case MSR_IA32_PL0_SSP ... MSR_IA32_INT_SSP_TAB: >+ if (!kvm_cet_is_msr_accessible(vcpu, msr_info)) >+ return 1; >+ if (is_noncanonical_address(data, vcpu)) >+ return 1; >+ if (!IS_ALIGNED(data, 4)) >+ return 1;
Why should MSR_IA32_INT_SSP_TAB be 4-byte aligned? I don't see this requirement in SDM.
IA32_INTERRUPT_SSP_TABLE_ADDR:
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when not 0) from the interrupt gate descriptor. (R/W) This MSR is not present on processors that do not support Intel 64 architecture. This field cannot represent a non-canonical address.
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