Messages in this thread Patch in this message | | | From | Drew Fustini <> | Date | Fri, 04 Aug 2023 20:14:46 -0700 | Subject | [PATCH RFC v2 2/4] riscv: dts: thead: Add TH1520 mmc controller and sdhci clock |
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Add nodes for the SDHCI fixed clock and the first mmc controller which is typically connected to the eMMC device.
Signed-off-by: Drew Fustini <dfustini@baylibre.com> --- arch/riscv/boot/dts/thead/th1520.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 56a73134b49e..b33bfb04c955 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -291,6 +298,16 @@ dmac0: dma-controller@ffefc00000 { status = "disabled"; }; + mmc0: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000 + 0xff 0xef014060 0x0 0x4>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sdhciirq"; + clocks = <&sdhci_clk>; + clock-names = "core"; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; -- 2.34.1
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