Messages in this thread | | | Date | Wed, 30 Aug 2023 14:10:08 +0530 | Subject | Re: [PATCH] clk: qcom: clk-rcg2: Fix wrong RCG clock rate for high parent frequencies | From | Devi Priya <> |
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On 7/21/2023 12:37 AM, Marijn Suijten wrote: > Can you retitle this to state "overflow" rather than just "wrong"? > That's more descriptive. > > E.g "Fix clockrate overflow for high parent frequencies" Sure okay > > On 2023-07-20 14:03:04, Devi Priya wrote: >> If the parent clock rate is greater than unsigned long max/2 then >> integer overflow happens when calculating the clock rate on 32-bit systems. >> As RCG2 uses half integer dividers, the clock rate is first being >> multiplied by 2 which will overflow the unsigned long max value. So, use >> unsigned long long for rate computations to avoid overflow. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> drivers/clk/qcom/clk-rcg2.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c >> index e22baf3a7112..42d00b134975 100644 >> --- a/drivers/clk/qcom/clk-rcg2.c >> +++ b/drivers/clk/qcom/clk-rcg2.c >> @@ -156,18 +156,18 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) >> * hid_div n >> */ >> static unsigned long >> -calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) >> +calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div) >> { >> + u64 rate = parent_rate; >> + >> if (hid_div) { >> rate *= 2; >> - rate /= hid_div + 1; >> + do_div(rate, hid_div + 1); > > I'm pretty sure mult_frac() could have solved this as well, without > temporarily going to u64? > > mult_frac(rate, 2, hid_div + 1)
Yes, sure will update > >> } >> >> if (mode) { >> - u64 tmp = rate; >> - tmp *= m; >> - do_div(tmp, n); >> - rate = tmp; >> + rate *= m; >> + do_div(rate, n); > > mult_frac(rate, m, n)
Will update in V2
Thanks, Devi Priya > > Or am I totally wrong? > > - Marijn > >> } >> >> return rate; >> -- >> 2.17.1 >>
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