Messages in this thread Patch in this message | | | From | MD Danish Anwar <> | Subject | [RFC PATCH net-next 1/2] dt-bindings: net: Add documentation for Half duplex support. | Date | Wed, 30 Aug 2023 17:01:33 +0530 |
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In order to support half-duplex operation at 10M and 100M link speeds, the PHY collision detection signal (COL) should be routed to ICSSG GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal and apply the CSMA/CD algorithm applicable for half duplex operation. A DT property, "ti,half-duplex-capable" is introduced for this purpose. If board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can be added to eth node of ICSSG, MII port to support half duplex operation at that port.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com> --- Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml index 13371159515a..59da9aeaee7e 100644 --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -107,6 +107,13 @@ properties: phandle to system controller node and register offset to ICSSG control register for RGMII transmit delay + ti,half-duplex-capable: + type: boolean + description: + Enable half duplex operation on ICSSG MII port. This requires + PHY output pin (COL) to be routed to ICSSG GPIO pin + (PRGx_PRU0/1_GPIO10) as input. + required: - reg anyOf: -- 2.34.1
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