Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH] x86/tdx: Mark TSC reliable | Date | Wed, 30 Aug 2023 09:33:47 +0200 |
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On Tue, Aug 29 2023 at 16:01, Jun Nakajima wrote: >> On Aug 25, 2023, at 10:09 AM, Thomas Gleixner <tglx@linutronix.de> wrote: >>> The newer spec says "Virtual TSC values are consistent among all the TD’s >>> VCPUs at the level supported by the CPU". >> >> That means what? It's not a guarantee for consistency either. :( > > Actually (in TDX Module 1.5 spec), the sentence is "Virtual TSC values > are consistent among all the TD’s VCPUs at the level supported by the > CPU, see below”. > > And the below: > --- > The host VMM is required to do the following: > • Set up the same IA32_TSC_ADJUST values on all LPs before initializing the Intel TDX module. > • Make sure IA32_TSC_ADJUST is not modified from its initial value before calling SEAMCALL. > > The Intel TDX module checks the above as part of TDH.VP.ENTER and any > other SEAMCALL leaf function that reads TSC.
What happens when the check detects that the host modified TSC ADJUST?
What validates the VMCS TSC offset field?
> The virtualized TSC is designed to have the following characteristics: > • The virtual TSC frequency is specified by the host VMM as an input > to TDH.MNG.INIT in units of 25MHz – it can be between 4 and 400 > (corresponding to a range of 100MHz to 10GHz).
What validates that the frequency is correct?
How is ensured that the host does not change TSC scaling?
Thanks,
tglx
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