lkml.org 
[lkml]   [2023]   [Aug]   [30]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v7 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge
    Date
    Add YAML dtschemas of Xilinx XDMA Soft IP PCIe Root Port Bridge
    dt binding.

    Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
    Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
    Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    Acked-by: Rob Herring <robh@kernel.org>
    ---
    changes in v7:
    - None
    changes in v6:
    - None
    change in v5:
    - Modified uppercase case hex value to lower case.
    change in v4:
    - Removed unnecessary space.
    changes in v3:
    - Fixed compatible string issue.
    - Modified ranges property description to maxItems.
    - Modified address-cell property of interrupt-controller child node.
    changes in v2:
    - None
    ---
    .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 114 +++++++++++++++++++++
    1 file changed, 114 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml

    diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
    new file mode 100644
    index 0000000..0aa00b8
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
    @@ -0,0 +1,114 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Xilinx XDMA PL PCIe Root Port Bridge
    +
    +maintainers:
    + - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
    +
    +allOf:
    + - $ref: /schemas/pci/pci-bus.yaml#
    +
    +properties:
    + compatible:
    + const: xlnx,xdma-host-3.00
    +
    + reg:
    + maxItems: 1
    +
    + ranges:
    + maxItems: 2
    +
    + interrupts:
    + items:
    + - description: interrupt asserted when miscellaneous interrupt is received.
    + - description: msi0 interrupt asserted when an MSI is received.
    + - description: msi1 interrupt asserted when an MSI is received.
    +
    + interrupt-names:
    + items:
    + - const: misc
    + - const: msi0
    + - const: msi1
    +
    + interrupt-map-mask:
    + items:
    + - const: 0
    + - const: 0
    + - const: 0
    + - const: 7
    +
    + interrupt-map:
    + maxItems: 4
    +
    + "#interrupt-cells":
    + const: 1
    +
    + interrupt-controller:
    + description: identifies the node as an interrupt controller
    + type: object
    + properties:
    + interrupt-controller: true
    +
    + "#address-cells":
    + const: 0
    +
    + "#interrupt-cells":
    + const: 1
    +
    + required:
    + - interrupt-controller
    + - "#address-cells"
    + - "#interrupt-cells"
    +
    + additionalProperties: false
    +
    +required:
    + - compatible
    + - reg
    + - ranges
    + - interrupts
    + - interrupt-map
    + - interrupt-map-mask
    + - "#interrupt-cells"
    + - interrupt-controller
    +
    +unevaluatedProperties: false
    +
    +examples:
    +
    + - |
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    + #include <dt-bindings/interrupt-controller/irq.h>
    +
    + soc {
    + #address-cells = <2>;
    + #size-cells = <2>;
    + pcie@a0000000 {
    + compatible = "xlnx,xdma-host-3.00";
    + reg = <0x0 0xa0000000 0x0 0x10000000>;
    + ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
    + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
    + #address-cells = <3>;
    + #size-cells = <2>;
    + #interrupt-cells = <1>;
    + device_type = "pci";
    + interrupt-parent = <&gic>;
    + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "misc", "msi0", "msi1";
    + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    + interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
    + <0 0 0 2 &pcie_intc_0 1>,
    + <0 0 0 3 &pcie_intc_0 2>,
    + <0 0 0 4 &pcie_intc_0 3>;
    + pcie_intc_0: interrupt-controller {
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + interrupt-controller;
    + };
    + };
    + };
    --
    1.8.3.1
    \
     
     \ /
      Last update: 2023-08-30 20:47    [W:3.468 / U:0.240 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site