Messages in this thread | | | Subject | Re: [PATCH v4 0/2] RISC-V: Probe for misaligned access speed | From | patchwork-bot+linux-riscv@kernel ... | Date | Wed, 30 Aug 2023 20:30:28 +0000 |
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Hello:
This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>:
On Fri, 18 Aug 2023 12:41:34 -0700 you wrote: > The current setting for the hwprobe bit indicating misaligned access > speed is controlled by a vendor-specific feature probe function. This is > essentially a per-SoC table we have to maintain on behalf of each vendor > going forward. Let's convert that instead to something we detect at > runtime. > > We have two assembly routines at the heart of our probe: one that > does a bunch of word-sized accesses (without aligning its input buffer), > and the other that does byte accesses. If we can move a larger number of > bytes using misaligned word accesses than we can with the same amount of > time doing byte accesses, then we can declare misaligned accesses as > "fast". > > [...]
Here is the summary with links: - [v4,1/2] RISC-V: Probe for unaligned access speed https://git.kernel.org/riscv/c/b98673c5b037 - [v4,2/2] RISC-V: alternative: Remove feature_probe_func https://git.kernel.org/riscv/c/b6e3f6e009a1
You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
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