Messages in this thread | | | Date | Fri, 4 Aug 2023 02:16:59 +0200 | From | Andrea Parri <> | Subject | Re: [RFC PATCH] membarrier: riscv: Provide core serializing command |
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> Can you double-check that riscv switch_mm() implies a fence.i or equivalent > on the CPU doing the switch_mm ?
AFAICT, (riscv) switch_mm() does not guarantee that.
> AFAIR membarrier use of sync_core_before_usermode relies on switch_mm > issuing a core serializing instruction.
I see. Thanks for the clarification.
BTW, the comment in __schedule() suggests that membarrier also relies on switch_mm() issuing a full memory barrier: I don't think this holds.
Removing the "deferred icache flush" logic in switch_mm() - in favour of a "plain" MB; FENCE.I - would meet both of these requirements.
Other ideas?
Andrea
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