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    Subject[PATCH 07/31] clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
    Date
    SCLK_SDMMC is the parent for SCLK_SDMMC_DRV and SCLK_SDMMC_SAMPLE, but
    used with the (more) correct name sclk_sdmmc. SD card tuning does currently
    fail as the parent can't be found under that name
    There is no need to suffix the name with '0' since RK312x SoCs do have a
    single sdmmc controller - so rename it to the name which is already used
    by it's children.

    Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
    Signed-off-by: Alex Bee <knaerzche@gmail.com>
    ---
    drivers/clk/rockchip/clk-rk3128.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
    index 17bacf6dd6e7..75071e0cd321 100644
    --- a/drivers/clk/rockchip/clk-rk3128.c
    +++ b/drivers/clk/rockchip/clk-rk3128.c
    @@ -310,7 +310,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
    GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
    RK2928_CLKGATE_CON(2), 15, GFLAGS),

    - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
    + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
    RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
    RK2928_CLKGATE_CON(2), 11, GFLAGS),

    --
    2.42.0
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