Messages in this thread | | | Date | Mon, 28 Aug 2023 10:27:34 +0800 | Subject | Re: [PATCH 1/1] mmc: Set optimal I/O size when mmc_setip_queue | From | Shawn Lin <> |
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Hi Sharp
On 2023/8/27 0:26, Sharp.Xia@mediatek.com wrote: > On Fri, 2023-08-25 at 17:17 +0800, Shawn Lin wrote: >> >>
After more testing, most of my platforms which runs at HS400/HS200 mode shows nearly no differences with the readahead ranging from 128 to 1024. Yet just a board shows a performance drop now. Highly suspect it's eMMC chip depends. I would recommand leave it to the BSP guys to decide which readahead value is best for their usage.
> > I tested with RK3568 and sdhci-of-dwcmshc.c driver, the performance improved by 2~3%. > > Before: > root@OpenWrt:/mnt/mmcblk0p3# time dd if=test.img of=/dev/null > 2097152+0 records in > 2097152+0 records out > real 0m 6.01s > user 0m 0.84s > sys 0m 2.89s > root@OpenWrt:/mnt/mmcblk0p3# cat /sys/block/mmcblk0/queue/read_ahead_kb > 128 > > After: > root@OpenWrt:/mnt/mmcblk0p3# echo 3 > /proc/sys/vm/drop_caches > root@OpenWrt:/mnt/mmcblk0p3# time dd if=test.img of=/dev/null > 2097152+0 records in > 2097152+0 records out > real 0m 5.86s > user 0m 1.04s > sys 0m 3.18s > root@OpenWrt:/mnt/mmcblk0p3# cat /sys/block/mmcblk0/queue/read_ahead_kb > 1024 > > root@OpenWrt:/sys/kernel/debug/mmc0# cat ios > clock: 200000000 Hz > actual clock: 200000000 Hz > vdd: 18 (3.0 ~ 3.1 V) > bus mode: 2 (push-pull) > chip select: 0 (don't care) > power mode: 2 (on) > bus width: 3 (8 bits) > timing spec: 9 (mmc HS200) > signal voltage: 1 (1.80 V) > driver type: 0 (driver type B) >
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