Messages in this thread | | | Date | Fri, 18 Aug 2023 09:15:53 +0200 | From | Michael Walle <> | Subject | Re: [PATCH v3] mtd: spi-nor: Check bus width while setting QE bit |
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> spi_nor_write_16bit_sr_and_check() should also check if bus width is > 4 before setting QE bit. > > Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on > lock()/unlock()") > Suggested-by: Michael Walle <michael@walle.cc> > Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
I'm not sure if the comment beneath needs an update, too.
In any case: Reviewed-by: Michael Walle <michael@walle.cc>
> --- > v2: > https://lore.kernel.org/lkml/20230816104245.2676965-1-hsinyi@chromium.org/ > --- > drivers/mtd/spi-nor/core.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 614960c7d22cc..1328128dfe65c 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -870,7 +870,9 @@ static int spi_nor_write_16bit_sr_and_check(struct > spi_nor *nor, u8 sr1) > ret = spi_nor_read_cr(nor, &sr_cr[1]); > if (ret) > return ret; > - } else if (nor->params->quad_enable) { > + } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 && > + spi_nor_get_protocol_width(nor->write_proto) == 4 && > + nor->params->quad_enable) { > /* > * If the Status Register 2 Read command (35h) is not > * supported, we should at least be sure we don't
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