Messages in this thread | | | From | Doug Anderson <> | Date | Wed, 16 Aug 2023 10:03:35 -0700 | Subject | Re: [PATCH v2,2/2] arm64: dts: mediatek: mt8183: set bus rx width to disable quad mode |
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Hi,
On Wed, Aug 16, 2023 at 3:43 AM Hsin-Yi Wang <hsinyi@chromium.org> wrote: > > Some of the SKUs are using gigadevice gd25lq64c flash chip. The chip > default enables quad mode, which results in the write protect pin set to > IO pin. In mt8183 kukui, we won't use quad enable for all SKUs, so apply > the property to disable spi nor's quad mode. > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi > index 6ce16a265e053..ef472b522f2e7 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi > @@ -877,6 +877,7 @@ w25q64dw: flash@0 { > compatible = "winbond,w25q64dw", "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <25000000>; > + spi-rx-bus-width = <2>;
This feels wrong to me. Is your controller actually capable of "dual SPI"? If so, why wasn't the rx-bus-width specified before? ...and if you're truly capable of "dual SPI" then why aren't you also setting the tx-bus-width?
My best guess (I can look up the schematic if needed) is that you're actually _single_ lane, not dual lane SPI. Thus, a more accurate description would probably be:
spi-rx-bus-width = <1>; spi-tx-bus-width = <1>;
...but... I think that the default of rx/tx bus width isn't specified is "1". Thus I think you should drop this patch.
-Doug
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