Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Wed, 16 Aug 2023 13:36:15 +0200 | Subject | Re: [PATCH] perf: ARM_SMMU_V3_PMU should depend on ARM_SMMU_V3 |
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Hi Robin,
On Wed, Aug 16, 2023 at 1:23 PM Robin Murphy <robin.murphy@arm.com> wrote: > On 2023-08-15 16:36, Geert Uytterhoeven wrote: > > There is no point in monitoring transactions passing through the SMMU > > when ARM Ltd. System MMU Version 3 (SMMUv3) Support is disabled. > > Hence replace the dependency on ARM64 by a dependency on ARM_SMMU_V3 > > (which implies the former). > > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > This caught my eye after commit 7c3f204e544dfa37 ("perf/smmuv3: Remove > > build dependency on ACPI") in arm64/for-next/core. > > > > Perhaps my understanding is wrong? Is there anything to monitor when > > ARM_SMMU_V3=n? > > Yes, at least TBU event 1 still counts bypass transactions even when the > SMMU is disabled, so PMCGs can be useful as basic traffic monitors in > their own right. Plus the original design intent was that PMCGs may also > be implemented by other things that interact with the SMMU, like > ATS-capable PCIe root complexes, or devices with their own internal > TLBs, thus they could potentially count any manner of > implementation-defined events that aren't necessarily related to SMMU > translation.
Thanks for the explanation! Hereby I withdraw my patch.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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