Messages in this thread | | | Date | Wed, 16 Aug 2023 14:23:25 +0530 | Subject | Re: [PATCH v1 3/3] PCI: qcom: Add OPP suuport for speed based performance state of RPMH | From | Krishna Chaitanya Chundru <> |
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On 8/16/2023 11:54 AM, Pavan Kondeti wrote: > On Tue, Aug 15, 2023 at 05:56:48PM +0530, Krishna chaitanya chundru wrote: >> Before link training vote for the maximum performance state of RPMH >> and once the link is up, vote for the performance state based upon >> the link speed. >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 61 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 61 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 7a87a47..e29a986 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -22,6 +22,7 @@ >> #include <linux/of_device.h> >> #include <linux/of_gpio.h> >> #include <linux/pci.h> >> +#include <linux/pm_opp.h> >> #include <linux/pm_runtime.h> >> #include <linux/platform_device.h> >> #include <linux/phy/pcie.h> >> @@ -1357,6 +1358,51 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) >> return 0; >> } >> >> +static void qcom_pcie_opp_update(struct qcom_pcie *pcie) >> +{ >> + struct dw_pcie *pci = pcie->pci; >> + struct dev_pm_opp *opp; >> + u32 offset, status; >> + uint32_t freq; >> + int speed; >> + int ret = 0; >> + >> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); >> + >> + /* Only update constraints if link is up. */ >> + if (!(status & PCI_EXP_LNKSTA_DLLLA)) >> + return; >> + >> + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); >> + >> + switch (speed) { >> + case 1: >> + freq = 2500000; >> + break; >> + case 2: >> + freq = 5000000; >> + break; >> + case 3: >> + freq = 8000000; >> + break; >> + default: >> + WARN_ON_ONCE(1); >> + fallthrough; >> + case 4: >> + freq = 16000000; >> + break; >> + } >> + >> + opp = dev_pm_opp_find_freq_exact(pci->dev, freq, true); >> + >> + if (!IS_ERR(opp)) { >> + ret = dev_pm_opp_get_voltage(opp); >> + dev_pm_opp_put(opp); >> + } >> + > Where are we setting the OPP here? > >> +} >> + >> static void qcom_pcie_icc_update(struct qcom_pcie *pcie) >> { >> struct dw_pcie *pci = pcie->pci; >> @@ -1439,8 +1485,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) >> static int qcom_pcie_probe(struct platform_device *pdev) >> { >> const struct qcom_pcie_cfg *pcie_cfg; >> + unsigned long max_freq = INT_MAX; >> struct device *dev = &pdev->dev; >> struct qcom_pcie *pcie; >> + struct dev_pm_opp *opp; >> struct dw_pcie_rp *pp; >> struct resource *res; >> struct dw_pcie *pci; >> @@ -1511,6 +1559,17 @@ static int qcom_pcie_probe(struct platform_device *pdev) >> if (ret) >> goto err_pm_runtime_put; >> >> + /* OPP table is optional */ >> + ret = devm_pm_opp_of_add_table(dev); >> + if (ret && ret != -ENODEV) { >> + dev_err(dev, "Invalid OPP table in Device tree\n"); >> + goto err_pm_runtime_put; >> + } >> + >> + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); >> + if (!IS_ERR(opp)) >> + dev_pm_opp_put(opp); >> + > This OPP (corresponding to max freq) is not used, so how are we voting > for max perf state during probe? > >> ret = pcie->cfg->ops->get_resources(pcie); >> if (ret) >> goto err_pm_runtime_put; >> @@ -1531,6 +1590,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) >> >> qcom_pcie_icc_update(pcie); >> >> + qcom_pcie_opp_update(pcie); >> + > commit description says, OPP voting is done as per the link speed after > probe? I don't see any calls to qcom_pcie_opp_update() outside probe.
my mistake dev_pm_opp_set_opp somehow missed here I will update in next patch.
- KC
>> if (pcie->mhi) >> qcom_pcie_init_debugfs(pcie); >> >> > Thanks, > Pavan
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