Messages in this thread | | | From | Michael Shavit <> | Date | Tue, 15 Aug 2023 13:20:04 +0800 | Subject | Re: [PATCH v5 5/9] iommu/arm-smmu-v3: Refactor write_ctx_desc |
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On Thu, Aug 10, 2023 at 11:39 PM Jason Gunthorpe <jgg@nvidia.com> wrote: > > Actually, I don't think this even works as nothing on the PASID path > adds to the list that arm_smmu_write_ctx_desc_devices() iterates over ?? > > Then the remaining two calls: > > arm_smmu_share_asid(struct mm_struct *mm, u16 asid) > arm_smmu_write_ctx_desc_devices(smmu_domain, 0, cd); > > This is OK only if the sketchy assumption that the CD > we extracted for a conflicting ASID is not asigned to a PASID. > > static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) > arm_smmu_write_ctx_desc_devices(smmu_domain, mm->pasid, &quiet_cd); > > This doesn't work because we didn't add the master to the list > during __arm_smmu_sva_bind and this path is expressly working > on the PASID binds, not the RID binds.
Actually it is working on the RID attached domain (as returned by iommu_get_domain_for_dev() at sva_bind time) not the SVA domain here... The arm SVA implementation completely dismisses the SVA handle (I also have a patch to fix this ;) . Need to find the time to polish and send out).
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