Messages in this thread | | | Date | Mon, 14 Aug 2023 07:57:51 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v1] clk: starfive: jh7110-sys: Set PLL0 rate to 1.5GHz |
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On Mon, Aug 14, 2023 at 11:06:05AM +0800, Xingyu Wu wrote: > On 2023/8/11 14:43, Conor Dooley wrote: > > On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote: > >> Set PLL0 rate to 1.5GHz. > > > > Why are you doing that though? > > Because the CPU frequency scaling is based on 1.5GHz rate on JH7110 SoC. > And now the PLL clock driver has been accepted and PLL0 is just 1GHz[1]. > [1] https://github.com/starfive-tech/VisionFive2/issues/55 > > We should set the PLL0 rate to a correct rate (1.5GHz) and then > the CPUfreq will work normally.
Please include an explanation in the commit message of the problem this is addressing.
Also, a Fixes: tag + reported-by?
> Best regards, > Xingyu Wu > > > > > > >> Change the parent of cpu_root clock > >> and the divider of cpu_core before setting. > >> > >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > >> --- > >> > >> Hi Stephen and Emil, > >> > >> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu > >> operation, the cpu_root's parent clock should be changed first. > >> And the divider of the cpu_core clock should be set to 2 so they > >> won't crash when setting 1.5GHz without voltage regulation. > >> > >> This patch is based on linux-next which has merge PLL driver on > >> StarFive JH7110 SoC. > >> > >> Thanks, > >> Xingyu Wu > [unhandled content-type:application/pgp-signature] | |