Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [patch V3a 30/40] x86/cpu: Provide an AMD/HYGON specific topology parser | Date | Fri, 11 Aug 2023 19:11:05 +0200 |
| |
On Fri, Aug 11 2023 at 20:58, Pu Wen wrote: > On 2023/8/3 3:51, Thomas Gleixner wrote: >> + if (tscan->c->x86_vendor == X86_VENDOR_AMD) { >> + if (tscan->c->x86 == 0x15) >> + tscan->c->topo.cu_id = leaf.cuid; >> + >> + cacheinfo_amd_init_llc_id(tscan->c, leaf.nodeid); >> + } else { >> + /* >> + * Package ID is ApicId[6..] on Hygon CPUs. See commit >> + * e0ceeae708ce for explanation. The topology info is >> + * screwed up: The package shift is always 6 and the node >> + * ID is bit [4:5]. Don't touch the latter without >> + * confirmation from the Hygon developers. >> + */ >> + topology_set_dom(tscan, TOPO_CORE_DOMAIN, 6, tscan->dom_ncpus[TOPO_CORE_DOMAIN]); > > Hygon updated CPUs will not always shift 6, and shift 6 is not good for > running guests. > So suggest to modify like this: > if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && tscan->c->x86_model <= > 0x3) > topology_set_dom(tscan, TOPO_CORE_DOMAIN, 6, > tscan->dom_ncpus[TOPO_CORE_DOMAIN]);
This is exactly what the existing code does today. Can you please send a delta patch on top of this with a proper explanation?
Thanks,
tglx
| |