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    SubjectRe: [PATCH 02/11] drm/bridge: tc358768: Fix bit updates
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    On 04/08/2023 13:44, Tomi Valkeinen wrote:
    > The driver has a few places where it does:
    >
    > if (thing_is_enabled_in_config)
    > update_thing_bit_in_hw()
    >
    > This means that if the thing is _not_ enabled, the bit never gets
    > cleared. This affects the h/vsyncs and continuous DSI clock bits.

    I guess the idea was to keep the reset value unless it needs to be flipped.

    >
    > Fix the driver to always update the bit.
    >
    > Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
    > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
    > ---
    > drivers/gpu/drm/bridge/tc358768.c | 13 +++++++------
    > 1 file changed, 7 insertions(+), 6 deletions(-)
    >
    > diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
    > index bc97a837955b..b668f77673c3 100644
    > --- a/drivers/gpu/drm/bridge/tc358768.c
    > +++ b/drivers/gpu/drm/bridge/tc358768.c
    > @@ -794,8 +794,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
    > val |= BIT(i + 1);
    > tc358768_write(priv, TC358768_HSTXVREGEN, val);
    >
    > - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
    > - tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
    > + tc358768_write(priv, TC358768_TXOPTIONCNTRL,
    > + (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
    >
    > /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
    > val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
    > @@ -861,11 +861,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
    > tc358768_write(priv, TC358768_DSI_HACT, hact);
    >
    > /* VSYNC polarity */
    > - if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
    > - tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
    > + tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
    > + (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);

    Was this the reverse before and should be:
    (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : BIT(5)

    > +
    > /* HSYNC polarity */
    > - if (mode->flags & DRM_MODE_FLAG_PHSYNC)
    > - tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
    > + tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
    > + (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
    >
    > /* Start DSI Tx */
    > tc358768_write(priv, TC358768_DSI_START, 0x1);
    >

    --
    Péter

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