Messages in this thread | | | From | "Rafael J. Wysocki" <> | Date | Tue, 1 Aug 2023 11:54:43 +0200 | Subject | Re: [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3 |
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On Sat, Jul 15, 2023 at 1:00 AM Limonciello, Mario <mario.limonciello@amd.com> wrote: > > > On 7/14/2023 2:17 PM, Rafael J. Wysocki wrote: > > Well, this looks like a spec interpretation difference. > > We thought that _SxD/_SxW would only be relevant for devices with ACPI > PM support, but the firmware people seem to think that those objects > are also relevant for PCI devices that don't have ACPI PM support > (because those devices are still power-manageable via PMCSR). If > Windows agrees with that viewpoint, we'll need to adjust, but not > through adding _SxW checks in random places. > > I think that depends upon how you want to handle the lack of _S0W.
If _S0W is not present, _S0D should return the deepest state that can be used.
If that is not present, it is a matter of OS policy.
> On these problematic devices there is no _S0W under the PCIe > root port. As I said; Windows puts them into D0 in this case though.
Do you know what the rationale for that is? Maybe Windows takes the lack of _S0W/_S0D as the indication that the device could not go into low-power states in D0, but do you actually know that this is the case?
Surely, for non-bridge devices the lack of _S0W/_S0D does not mean that the device should not be programmed into low-power states via PMCSR, but maybe Root Ports are an exception?
> So acpi_dev_power_state_for_wake should return ACPI_STATE_UNKNOWN.
And then who'll decide what to do with that return value?
> Can you suggest where you think adding a acpi_dev_power_state_for_wake() does make sense? > > Two areas that I think would work would be in: pci_pm_suspend_noirq() (to avoid calling pci_prepare_to_sleep) > > or > > directly in pci_prepare_to_sleep() to check that value in lieu of pci_target_state().
I'm not sure that this is a core problem TBH. It looks like this is an exception made specifically for ports, so this check seems to belong to where ports are handled, so that would be acpi_pci_bridge_d3() after all.
However, _S0D needs to be checked too when _S0W is not present.
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