Messages in this thread | | | From | WANG Rui <> | Date | Tue, 1 Aug 2023 17:30:33 +0800 | Subject | Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier |
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Hello,
On Tue, Aug 1, 2023 at 4:32 PM Will Deacon <will@kernel.org> wrote: > > Hmm, somehow this one passed me by, but I think that puts you in the naughty > corner with Itanium. It probably also means your READ_ONCE() is broken, > unless the compiler emits barriers for volatile reads (like ia64)?
Hmm, I agree with your perspective. Allowing out-of-order loads for the same address in the memory model provides certain performance benefits, but it also poses challenges to software. Fortunately, hardware supports software to disable this feature when needed.
Regards, -- WANG Rui
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