Messages in this thread | | | Date | Tue, 1 Aug 2023 21:45:16 +0200 | From | Marco Felsch <> | Subject | Re: [PATCH] clk: imx: composite-8m: avoid glitches when set_rate would be a no-op |
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On 23-08-01, Ahmad Fatoum wrote: > Reconfiguring the clock divider to the exact same value is observed > on an i.MX8MN to often cause a short clock pause, probably because > the divider restarts counting from the time the register is written. > > This issue doesn't show up normally, because the clock framework will > take care to not call set_rate when the clock rate is the same. > However, when we configure an upstream clock (e.g. an audio_pll), the > common code will call set_rate with the newly calculated rate on all > children. As the new rate is different, we enter set_rate and compute > the same divider values, write them back and cause the glitch (e.g. > on a SAI's MCLK). > > To avoid the glitch, we skip writing the same value back again. > > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
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