Messages in this thread | | | From | Fabio Estevam <> | Date | Thu, 6 Jul 2023 10:22:12 -0300 | Subject | Re: [PATCH] ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for master mode |
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Hi Andreas,
On Thu, Jul 6, 2023 at 9:34 AM Andreas Henriksson <andreas@fatal.se> wrote:
> I think your initial review comment was spot on Fabio. There probably > needs to be a(n imx8mm) specific flag that says when this workaround > should be applied and gate the code in bclk function on that. > Atleast that's the only thing I can think of if my interpretation of the > problem for imx8mm is correct.
Yes, deciding whether MCLK_EN should act as a clock gate based on the number of SAI registers seems fragile to me.
I have sent a proposal as RFC. Please give it a try if you have a chance.
I would like Shengjiu to confirm if imx8mn and imx93 should also behave like imx8mm in this aspect.
Cheers
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