Messages in this thread | | | Date | Thu, 6 Jul 2023 16:21:05 +0530 | Subject | Re: [PATCH V2 3/5] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version | From | Imran Shaik <> |
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On 6/28/2023 4:36 PM, Konrad Dybcio wrote: > On 28.06.2023 11:28, Imran Shaik wrote: >> Add support for gcc_ddrss_ecpri_gsi_clk and update the GCC clkref clocks >> as per the latest hardware version of QDU1000 and QRU100 SoCs. >> >> Co-developed-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> >> --- >> Changes since v1: >> - Newly added >> >> drivers/clk/qcom/gcc-qdu1000.c | 32 ++++++++++++++++++++++++++------ >> 1 file changed, 26 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c >> index c00d26a3e6df..991fb2bc97e9 100644 >> --- a/drivers/clk/qcom/gcc-qdu1000.c >> +++ b/drivers/clk/qcom/gcc-qdu1000.c >> @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { >> }, >> }; >> >> +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { >> + .halt_reg = 0x54298, >> + .halt_check = BRANCH_HALT_VOTED, >> + .hwcg_reg = 0x54298, >> + .hwcg_bit = 1, >> + .clkr = { >> + .enable_reg = 0x54298, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ddrss_ecpri_gsi_clk", >> + .parent_hws = (const struct clk_hw*[]) { >> + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_aon_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_ecpri_ahb_clk = { >> .halt_reg = 0x3a008, >> .halt_check = BRANCH_HALT_VOTED, >> @@ -1447,14 +1467,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { >> >> static struct clk_branch gcc_pcie_0_clkref_en = { >> .halt_reg = 0x9c004, >> - .halt_bit = 31, >> - .halt_check = BRANCH_HALT_ENABLE, >> + .halt_check = BRANCH_HALT, >> .clkr = { >> .enable_reg = 0x9c004, >> .enable_mask = BIT(0), >> .hw.init = &(const struct clk_init_data) { >> .name = "gcc_pcie_0_clkref_en", >> - .ops = &clk_branch_ops, >> + .ops = &clk_branch2_ops, > This sounds like a separate fix, clk_branch_ops seems to only concern > 10+yo chips. > > Konrad
Sure, will split this patch and push the next series.
Thanks, Imran
>> }, >> }, >> }; >> @@ -2274,14 +2293,13 @@ static struct clk_branch gcc_tsc_etu_clk = { >> >> static struct clk_branch gcc_usb2_clkref_en = { >> .halt_reg = 0x9c008, >> - .halt_bit = 31, >> - .halt_check = BRANCH_HALT_ENABLE, >> + .halt_check = BRANCH_HALT, >> .clkr = { >> .enable_reg = 0x9c008, >> .enable_mask = BIT(0), >> .hw.init = &(const struct clk_init_data) { >> .name = "gcc_usb2_clkref_en", >> - .ops = &clk_branch_ops, >> + .ops = &clk_branch2_ops, >> }, >> }, >> }; >> @@ -2523,6 +2541,8 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { >> [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, >> [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, >> [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, >> + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, >> + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, >> }; >> >> static const struct qcom_reset_map gcc_qdu1000_resets[] = {
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