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    SubjectRe: [PATCH v1 5/6] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes
    From
    On 5.07.2023 10:17, Mrinmay Sarkar wrote:
    > Add pcie dtsi nodes for two controllers found on sa8775p platform.
    >
    > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
    > ---[...]

    > + pcie1_phy: phy@1c14000 {
    > + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
    > + reg = <0x0 0x1c14000 0x0 0x4000>;
    > +
    > + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
    > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
    > + <&gcc GCC_PCIE_CLKREF_EN>,
    > + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
    > + <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
    > + <&gcc GCC_PCIE_1_PIPE_CLK>,
    > + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
    > +
    > + clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
    > + "pipe", "pipediv2";
    > +
    > + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
    > + assigned-clock-rates = <100000000>;
    > +
    > + power-domains = <&gcc PCIE_1_GDSC>;
    Please check if it's the correct power domain. I've heard that the PCIe PHY
    may be hooked up to something else but have no way of confirming myself.

    Konrad
    > +
    > + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
    > + reset-names = "phy";
    > +
    > + #clock-cells = <0>;
    > + clock-output-names = "pcie_1_pipe_clk";
    > +
    > + #phy-cells = <0>;
    > +
    > + status = "disabled";
    > +
    > + };
    > };

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