Messages in this thread Patch in this message | | | Date | Fri, 7 Jul 2023 03:24:12 +0300 | Subject | Re: [PATCH v4 6/6] drm/msm/dpu: Update dev core dump to dump registers of sub-blocks | From | Dmitry Baryshkov <> |
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On 06/07/2023 23:48, Ryan McCann wrote: > Currently, the device core dump mechanism does not dump registers of > sub-blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Edit > dpu_kms_mdp_snapshot function to account for sub-blocks. > > Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 66 ++++++++++++++++++++++++++++++--- > 1 file changed, 60 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 70dbb1204e6c..afc45d597d65 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -903,25 +903,58 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > cat->ctl[i].base, cat->ctl[i].name); > > /* dump DSPP sub-blocks HW regs info */ > - for (i = 0; i < cat->dspp_count; i++) > + for (i = 0; i < cat->dspp_count; i++) { > msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, dpu_kms->mmio + > cat->dspp[i].base, cat->dspp[i].name); > > + if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) > + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, > + dpu_kms->mmio + cat->dspp[i].base + > + cat->dspp[i].sblk->pcc.base, "%s_%s",
This might look simpler in the following form. Could you please consider it?
void *base = dpu_kms + cat->dspp[i].base;
msm_disp_snapshot_add_block(..., base, cat->dspp[i].name)
if (!cat->dspp[i].sblk) continue;
if (cat->dspp[i].sblk->pcc.len) msm_disp_snapshot_add_block(..., base + cat->dspp[i].sblk->pcc.base, ...);
> + cat->dspp[i].name, > + cat->dspp[i].sblk->pcc.name); > + } > + > /* dump INTF sub-blocks HW regs info */ > for (i = 0; i < cat->intf_count; i++) > msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, dpu_kms->mmio + > cat->intf[i].base, cat->intf[i].name); > > /* dump PP sub-blocks HW regs info */ > - for (i = 0; i < cat->pingpong_count; i++) > + for (i = 0; i < cat->pingpong_count; i++) { > msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, dpu_kms->mmio + > cat->pingpong[i].base, cat->pingpong[i].name); > > + /* TE2 block has length of 0, so will not print it */ > + > + if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) > + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, > + dpu_kms->mmio + cat->pingpong[i].base + > + cat->pingpong[i].sblk->dither.base, "%s_%s", > + cat->pingpong[i].name, > + cat->pingpong[i].sblk->dither.name); > + } > + > /* dump SSPP sub-blocks HW regs info */ > - for (i = 0; i < cat->sspp_count; i++) > + for (i = 0; i < cat->sspp_count; i++) { > msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, dpu_kms->mmio + > cat->sspp[i].base, cat->sspp[i].name); > > + if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) > + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, > + dpu_kms->mmio + cat->sspp[i].base + > + cat->sspp[i].sblk->scaler_blk.base, "%s_%s", > + cat->sspp[i].name, > + cat->sspp[i].sblk->scaler_blk.name); > + > + if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) > + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, > + dpu_kms->mmio + cat->sspp[i].base + > + cat->sspp[i].sblk->csc_blk.base, "%s_%s", > + cat->sspp[i].name, > + cat->sspp[i].sblk->csc_blk.name); > + } > + > /* dump LM sub-blocks HW regs info */ > for (i = 0; i < cat->mixer_count; i++) > msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, dpu_kms->mmio + > @@ -943,9 +976,30 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > } > > /* dump DSC sub-blocks HW regs info */ > - for (i = 0; i < cat->dsc_count; i++) > - msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, dpu_kms->mmio + > - cat->dsc[i].base, cat->dsc[i].name); > + for (i = 0; i < cat->dsc_count; i++) { > + if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { > + struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; > + struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; > + > + /* For now, pass in a length of 0 because the DSC_BLK register space > + * overlaps with the sblks' register space. > + * > + * TODO: Pass in a length of 0 to DSC_BLK_1_2 in the HW catalog where > + * applicable.
Please assume that https://patchwork.freedesktop.org/series/119776/ and rebase your code on top of it.
> + */ > + msm_disp_snapshot_add_block(disp_state, 0, dpu_kms->mmio + > + cat->dsc[i].base, cat->dsc[i].name); > + msm_disp_snapshot_add_block(disp_state, enc.len, dpu_kms->mmio + > + cat->dsc[i].base + enc.base, "%s_%s", > + cat->dsc[i].name, enc.name); > + msm_disp_snapshot_add_block(disp_state, ctl.len, dpu_kms->mmio + > + cat->dsc[i].base + ctl.base, "%s_%s", > + cat->dsc[i].name, ctl.name); > + } else { > + msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, dpu_kms->mmio + > + cat->dsc[i].base, cat->dsc[i].name); > + } > + } > > pm_runtime_put_sync(&dpu_kms->pdev->dev); > } >
-- With best wishes Dmitry
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