Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 4 Jul 2023 17:36:03 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v4 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI |
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Hey William,
On Tue, Jul 04, 2023 at 05:04:52PM +0800, William Qiu wrote: > Add QSPI clock operation in device probe. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/
These Reported-by tags don't seem correct, given they were reports about this patch, not the reason for it - but did you actually check that you fixed the errors that the patch produces?
This particular one seems to complain about a hunk that is still in the patch & the CI running on the RISC-V patchwork is complaining about it.
Cheers, Conor.
> @@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev) > struct spi_master *master = dev_get_drvdata(dev); > > clk_prepare_enable(cqspi->clk); > + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) > + clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); > cqspi_wait_idle(cqspi); > cqspi_controller_init(cqspi); > > -- > 2.34.1 > [unhandled content-type:application/pgp-signature] | ![\](/images/icornerr.gif) |