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    SubjectRe: [PATCH v2 3/5] mm: Default implementation of arch_wants_pte_order()
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    On 7/4/2023 11:59 AM, Yu Zhao wrote:
    > On Mon, Jul 3, 2023 at 9:02 PM Yu Zhao <yuzhao@google.com> wrote:
    >>
    >> On Mon, Jul 3, 2023 at 8:23 PM Yin, Fengwei <fengwei.yin@intel.com> wrote:
    >>>
    >>>
    >>>
    >>> On 7/3/2023 9:53 PM, Ryan Roberts wrote:
    >>>> arch_wants_pte_order() can be overridden by the arch to return the
    >>>> preferred folio order for pte-mapped memory. This is useful as some
    >>>> architectures (e.g. arm64) can coalesce TLB entries when the physical
    >>>> memory is suitably contiguous.
    >>>>
    >>>> The first user for this hint will be FLEXIBLE_THP, which aims to
    >>>> allocate large folios for anonymous memory to reduce page faults and
    >>>> other per-page operation costs.
    >>>>
    >>>> Here we add the default implementation of the function, used when the
    >>>> architecture does not define it, which returns the order corresponding
    >>>> to 64K.
    >>>>
    >>>> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
    >>>> ---
    >>>> include/linux/pgtable.h | 13 +++++++++++++
    >>>> 1 file changed, 13 insertions(+)
    >>>>
    >>>> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
    >>>> index a661a17173fa..f7e38598f20b 100644
    >>>> --- a/include/linux/pgtable.h
    >>>> +++ b/include/linux/pgtable.h
    >>>> @@ -13,6 +13,7 @@
    >>>> #include <linux/errno.h>
    >>>> #include <asm-generic/pgtable_uffd.h>
    >>>> #include <linux/page_table_check.h>
    >>>> +#include <linux/sizes.h>
    >>>>
    >>>> #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
    >>>> defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
    >>>> @@ -336,6 +337,18 @@ static inline bool arch_has_hw_pte_young(void)
    >>>> }
    >>>> #endif
    >>>>
    >>>> +#ifndef arch_wants_pte_order
    >>>> +/*
    >>>> + * Returns preferred folio order for pte-mapped memory. Must be in range [0,
    >>>> + * PMD_SHIFT-PAGE_SHIFT) and must not be order-1 since THP requires large folios
    >>>> + * to be at least order-2.
    >>>> + */
    >>>> +static inline int arch_wants_pte_order(struct vm_area_struct *vma)
    >>>> +{
    >>>> + return ilog2(SZ_64K >> PAGE_SHIFT);
    >>> Default value which is not related with any silicon may be: PAGE_ALLOC_COSTLY_ORDER?
    >>>
    >>> Also, current pcp list support cache page with order 0...PAGE_ALLOC_COSTLY_ORDER, 9.
    >>> If the pcp could cover the page, the pressure to zone lock will be reduced by pcp.
    >>
    >> The value of PAGE_ALLOC_COSTLY_ORDER is reasonable but again it's a
    >> s/w policy not a h/w preference. Besides, I don't think we can include
    >> mmzone.h in pgtable.h.
    >
    > I think we can make a compromise:
    > 1. change the default implementation of arch_has_hw_pte_young() to return 0, and
    > 2. in memory.c, we can try PAGE_ALLOC_COSTLY_ORDER for archs that
    > don't override arch_has_hw_pte_young(), or if its return value is too
    > large to fit.
    Do you mean arch_wants_pte_order()? Yes. This looks good to me. Thanks.


    Regards
    Yin, Fengwei

    > This should also take care of the regression, right?

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