Messages in this thread | | | Date | Mon, 31 Jul 2023 14:59:13 +0200 | From | Florian Eckert <> | Subject | Re: [PATCH 2/2] dt-bindings: clock: intel,cgu-lgm: add mxl,control-gate option |
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Thanks for your reply,
> You described the desired Linux feature or behavior, not the actual > hardware. The bindings are about the latter, so instead you need to > rephrase the property and its description to match actual hardware > capabilities/features/configuration etc.
You have correctly identified that this is not a hardware configuration, but a driver configuration. Currently, the driver is configured so that the gates cannot be switched via the clk subsystem callbacks. When registering the data structures from the driver, I have to pass a flag GATE_CLK_HW so that the gate is managed by the driver.
I didn't want to always change the source of the driver when it has to take care of the GATE, so I wanted to map this via the dts.
I have a board support package from Maxlinear for the Lightning Mountain Soc with other drivers that are not upstream now. Some of them use the clock framework some of them does not.
Due to missing documents it is not possible to send these drivers upstream. Strictly speaking, this is about the gptc and the watchdog.
Since it is a buildin_platform driver, it can also not work via module parameters.
Best regards
Florian
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