Messages in this thread Patch in this message | | | Date | Mon, 31 Jul 2023 10:19:33 -0000 | From | "tip-bot2 for Ravi Bangoria" <> | Subject | [tip: perf/core] perf/mem: Introduce PERF_MEM_LVLNUM_UNC |
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The following commit has been merged into the perf/core branch of tip:
Commit-ID: 526fffabc5fb63e80eb890c74b6570df2570c87f Gitweb: https://git.kernel.org/tip/526fffabc5fb63e80eb890c74b6570df2570c87f Author: Ravi Bangoria <ravi.bangoria@amd.com> AuthorDate: Tue, 25 Jul 2023 20:32:04 +05:30 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Wed, 26 Jul 2023 12:28:44 +02:00
perf/mem: Introduce PERF_MEM_LVLNUM_UNC
Older API PERF_MEM_LVL_UNC can be replaced by PERF_MEM_LVLNUM_UNC.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230725150206.184-2-ravi.bangoria@amd.com --- include/uapi/linux/perf_event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 3767543..39c6a25 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1339,7 +1339,8 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0x8 available */ +/* 5-0x7 available */ +#define PERF_MEM_LVLNUM_UNC 0x08 /* Uncached */ #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
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