Messages in this thread | | | From | Zong Li <> | Date | Tue, 1 Aug 2023 08:37:56 +0800 | Subject | Re: [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues |
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On Tue, Aug 1, 2023 at 7:35 AM Nick Kossifidis <mick@ics.forth.gr> wrote: > > On 7/31/23 16:15, Zong Li wrote: > > On Mon, Jul 31, 2023 at 5:32 PM Nick Kossifidis <mick@ics.forth.gr> wrote: > >> > >> On 7/29/23 15:58, Zong Li wrote: > >>> On Thu, Jul 20, 2023 at 3:34 AM Tomasz Jeznach <tjeznach@rivosinc.com> wrote: > >>>> + iommu->cap = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAP); > >>>> + > >>>> + /* For now we only support WSIs until we have AIA support */ > >>> > >>> I'm not completely understand AIA support here, because I saw the pci > >>> case uses the MSI, and kernel seems to have the AIA implementation. > >>> Could you please elaborate it? > >>> > >> > >> When I wrote this we didn't have AIA in the kernel, and without IMSIC we > >> can't have MSIs in the hart (we can still have MSIs in the PCIe controller). > > > > Thanks for your clarification, do we support the MSI in next version? > > > > I don't think there is an IOMMU implementation out there (emulated or in > hw) that can do MSIs and is not a pcie device (the QEMU implementation > is a pcie device). If we have something to test this against, and we > also have an IMSIC etc, we can work on that.
I guess I can assist with that. We have an IOMMU hardware (non-pcie device) that has already implemented the MSI functionality, and I have conducted testing on it. Perhaps let me add the related implementation here after this series is merged.
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