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    SubjectRe: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
    пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <jernej.skrabec@gmail.com>:
    >
    > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
    > > Add pinmux node that describes pins on PC port which required for
    > > QSPI mode.
    > >
    > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
    > > ---
    > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
    > > 1 file changed, 7 insertions(+)
    > >
    > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
    > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
    > > 1bb1e5cae602..9f754dd03d85 100644
    > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
    > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
    > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
    > > pins = "PB6", "PB7";
    > > function = "uart3";
    > > };
    > > +
    > > + /omit-if-no-ref/
    > > + qspi0_pc_pins: qspi0-pc-pins {
    > > + pins = "PC2", "PC3", "PC4", "PC5",
    > "PC6",
    > > + "PC7";
    > > + function = "spi0";
    > > + };
    >
    > Sorry for late review, but it seems I'm missing something. D1 manual says
    > those are pins for ordinary SPI, with HOLD and WP signals. Can they be
    > repurposed for quad SPI?
    >
    Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI
    Quad-Input/Quad-Output Mode):
    "Using the quad mode allows data to be transferred to or from the
    device at 4 times the rate of standard single mode, the data can be
    read
    at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3
    (HOLD#)) at the same time."

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