Messages in this thread | | | From | Andy Shevchenko <> | Date | Fri, 28 Jul 2023 12:46:28 +0300 | Subject | Re: [PATCH v3 07/42] soc: Add SoC driver for Cirrus ep93xx |
| |
On Fri, Jul 28, 2023 at 12:28 PM Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > Hello Andy! > > On Fri, 2023-07-21 at 17:13 +0300, Andy Shevchenko wrote: > > On Thu, Jul 20, 2023 at 02:29:07PM +0300, Nikita Shubin via B4 Relay > > wrote: > > > From: Nikita Shubin <nikita.shubin@maquefel.me> > > > + spin_lock_irqsave(&ep93xx_swlock, flags); > > > + > > > + regmap_read(map, EP93XX_SYSCON_DEVCFG, &val); > > > + val &= ~clear_bits; > > > + val |= set_bits; > > > + regmap_write(map, EP93XX_SYSCON_SWLOCK, > > > EP93XX_SWLOCK_MAGICK); > > > + regmap_write(map, EP93XX_SYSCON_DEVCFG, val); > > > > Is this sequence a must? > > I.o.w. can you first supply magic and then update devcfg? > > > > Unfortunately it is a must to write EP93XX_SYSCON_SWLOCK and only then > the next write to swlocked registers will succeed.
This doesn't answer my question. Can you first write a magic and then _update_ the other register (update means RMW op)?
-- With Best Regards, Andy Shevchenko
| |