Messages in this thread | | | Date | Wed, 19 Jul 2023 12:03:44 +0530 | Subject | Re: [PATCH v9 4/4] PCI: qcom-ep: Add ICC bandwidth voting support | From | Krishna Chaitanya Chundru <> |
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On 7/19/2023 10:04 AM, Manivannan Sadhasivam wrote: > On Tue, Jul 18, 2023 at 08:50:45PM +0530, Krishna chaitanya chundru wrote: >> Add support for voting interconnect (ICC) bandwidth based >> on the link speed and width. >> >> This commit is inspired from the basic interconnect support added >> to pcie-qcom driver in commit c4860af88d0c ("PCI: qcom: Add basic >> interconnect support"). >> >> The interconnect support is kept optional to be backward compatible >> with legacy devicetrees. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > You forgot to add my reviewed-by tag: > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > - Mani
Yeah I forgot it I will add in next patch.
- KC
> >> --- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 72 +++++++++++++++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index 0fe7f06..cf9fc94 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -13,6 +13,7 @@ >> #include <linux/debugfs.h> >> #include <linux/delay.h> >> #include <linux/gpio/consumer.h> >> +#include <linux/interconnect.h> >> #include <linux/mfd/syscon.h> >> #include <linux/phy/pcie.h> >> #include <linux/phy/phy.h> >> @@ -28,6 +29,7 @@ >> #define PARF_SYS_CTRL 0x00 >> #define PARF_DB_CTRL 0x10 >> #define PARF_PM_CTRL 0x20 >> +#define PARF_PM_STTS 0x24 >> #define PARF_MHI_CLOCK_RESET_CTRL 0x174 >> #define PARF_MHI_BASE_ADDR_LOWER 0x178 >> #define PARF_MHI_BASE_ADDR_UPPER 0x17c >> @@ -133,6 +135,11 @@ >> #define CORE_RESET_TIME_US_MAX 1005 >> #define WAKE_DELAY_US 2000 /* 2 ms */ >> >> +#define PCIE_GEN1_BW_MBPS 250 >> +#define PCIE_GEN2_BW_MBPS 500 >> +#define PCIE_GEN3_BW_MBPS 985 >> +#define PCIE_GEN4_BW_MBPS 1969 >> + >> #define to_pcie_ep(x) dev_get_drvdata((x)->dev) >> >> enum qcom_pcie_ep_link_status { >> @@ -178,6 +185,8 @@ struct qcom_pcie_ep { >> struct phy *phy; >> struct dentry *debugfs; >> >> + struct icc_path *icc_mem; >> + >> struct clk_bulk_data *clks; >> int num_clks; >> >> @@ -253,8 +262,49 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) >> disable_irq(pcie_ep->perst_irq); >> } >> >> +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) >> +{ >> + struct dw_pcie *pci = &pcie_ep->pci; >> + u32 offset, status, bw; >> + int speed, width; >> + int ret; >> + >> + if (!pcie_ep->icc_mem) >> + return; >> + >> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); >> + >> + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); >> + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); >> + >> + switch (speed) { >> + case 1: >> + bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); >> + break; >> + case 2: >> + bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); >> + break; >> + case 3: >> + bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); >> + break; >> + default: >> + dev_warn(pci->dev, "using default GEN4 bandwidth\n"); >> + fallthrough; >> + case 4: >> + bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); >> + break; >> + } >> + >> + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); >> + if (ret) >> + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", >> + ret); >> +} >> + >> static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) >> { >> + struct dw_pcie *pci = &pcie_ep->pci; >> int ret; >> >> ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); >> @@ -277,8 +327,24 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) >> if (ret) >> goto err_phy_exit; >> >> + /* >> + * Some Qualcomm platforms require interconnect bandwidth constraints >> + * to be set before enabling interconnect clocks. >> + * >> + * Set an initial peak bandwidth corresponding to single-lane Gen 1 >> + * for the pcie-mem path. >> + */ >> + ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); >> + if (ret) { >> + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", >> + ret); >> + goto err_phy_off; >> + } >> + >> return 0; >> >> +err_phy_off: >> + phy_power_off(pcie_ep->phy); >> err_phy_exit: >> phy_exit(pcie_ep->phy); >> err_disable_clk: >> @@ -289,6 +355,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) >> >> static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) >> { >> + icc_set_bw(pcie_ep->icc_mem, 0, 0); >> phy_power_off(pcie_ep->phy); >> phy_exit(pcie_ep->phy); >> clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); >> @@ -550,6 +617,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, >> if (IS_ERR(pcie_ep->phy)) >> ret = PTR_ERR(pcie_ep->phy); >> >> + pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); >> + if (IS_ERR(pcie_ep->icc_mem)) >> + ret = PTR_ERR(pcie_ep->icc_mem); >> + >> return ret; >> } >> >> @@ -573,6 +644,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) >> } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { >> dev_dbg(dev, "Received BME event. Link is enabled!\n"); >> pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; >> + qcom_pcie_ep_icc_update(pcie_ep); >> pci_epc_bme_notify(pci->ep.epc); >> } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { >> dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); >> -- >> 2.7.4 >>
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