Messages in this thread | | | Date | Sat, 1 Jul 2023 16:34:15 +0200 | From | Andrew Lunn <> | Subject | Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down |
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> Hi Andrew, > This block includes MII and MMD1 registers, which mainly configure the PLL > clocks, reset and calibration of the interface sgmii, there is no related > Clause 73 control register in this block.
O.K. What does it have in the MII ID registers? Does Linux think it is a PHY and instantiating an generic PHY driver for it?
Andrew
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