Messages in this thread | | | Date | Wed, 7 Jun 2023 10:07:49 -0400 | Subject | Re: [PATCH] EDAC/mce_amd: Remove SMCA Extended Error code descriptions | From | Yazen Ghannam <> |
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On 5/23/23 4:55 AM, Muralidhara M K wrote: > From: Muralidhara M K <muralidhara.mk@amd.com> > > On AMD systems with Scalable MCA, each machine check error of a SMCA bank > type has an associated bit position in the bank's control (CTL) register. > > An error's bit position in the CTL register is used during error decoding > for offsetting into the corresponding bank's error description structure. > As new errors are being added in newer AMD systems for existing SMCA bank > types, the underlying SMCA architecture guarantees that the bit positions > of existing errors are not altered. > > However, on some AMD systems some of the existing bit definitions in the > CTL register of SMCA bank type are reassigned without defining new HWID > and McaType. Consequently, the errors whose bit definitions have been > reassigned in the CTL register are being erroneously decoded. > > Remove SMCA Extended Error Code descriptions. This avoids decoding issues > for incorrectly reassigned bits, and avoids the related maintenance burden > in the kernel. This decoding can be done in external tools or by referring > to AMD documentation. The bank type and Extended Error Code value for an > error will continue to be printed as a convenience >
Minor nit: there should be a (.) at the end of the last sentence.
> Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> > --- > drivers/edac/mce_amd.c | 480 ----------------------------------------- > 1 file changed, 480 deletions(-) >
This patch is completely within EDAC, so it's not necessary to copy the x86 or TIP maintainers.
Also, this patch was sent in-reply-to another patch that is not related. Each of these can be sent independently.
Otherwise, this looks good to me.
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Thanks, Yazen
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