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    SubjectRe: [PATCH v8 29/33] x86/fred: allow FRED systems to use interrupt vectors 0x10-0x1f
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    On Mon, Apr 10 2023 at 01:14, Xin Li wrote:
    > From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
    >
    > FRED inherits the Intel VT-x enhancement of classified events with
    > a two-level event dispatch logic. The first-level dispatch is on
    > the event type, and the second-level is on the event vector. This
    > also means that vectors in different event types are orthogonal,
    > thus, vectors 0x10-0x1f become available as hardware interrupts.
    >
    > Enable interrupt vectors 0x10-0x1f on FRED systems (interrupt 0x80 is
    > already enabled.) Most of these changes are about removing the
    > assumption that the lowest-priority vector is hard-wired to 0x20.

    I'm not really interested in this again premature optimization.

    Can we please clarify how the final result of FRED vector layout will
    look like?

    I rather give up on reclaiming these 16 vectors than making _all_ system
    vectors dynamically assignable to avoid an extra partitioning of the
    vector space.

    Thanks,

    tglx

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