Messages in this thread | | | Date | Fri, 30 Jun 2023 12:59:47 -0700 | Subject | Re: [PATCH V10 2/5] PCI: Create device tree node for bridge | From | Lizhi Hou <> |
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On 6/30/23 09:48, Bjorn Helgaas wrote: > On Thu, Jun 29, 2023 at 05:52:26PM -0600, Rob Herring wrote: >> On Thu, Jun 29, 2023 at 05:56:31PM -0500, Bjorn Helgaas wrote: >>> On Thu, Jun 29, 2023 at 10:19:47AM -0700, Lizhi Hou wrote: >>>> The PCI endpoint device such as Xilinx Alveo PCI card maps the register >>>> spaces from multiple hardware peripherals to its PCI BAR. Normally, >>>> the PCI core discovers devices and BARs using the PCI enumeration process. >>>> There is no infrastructure to discover the hardware peripherals that are >>>> present in a PCI device, and which can be accessed through the PCI BARs. >>> IIUC this is basically a multi-function device except that instead of >>> each device being a separate PCI Function, they all appear in a single >>> Function. That would mean all the devices share the same config space >>> so a single PCI Command register controls all of them, they all share >>> the same IRQs (either INTx or MSI/MSI-X), any MMIO registers are likely >>> in a shared BAR, etc., right? >> Could be multiple BARs, but yes. > Where does the PCI glue live? E.g., who ioremaps the BARs? Who sets > up PCI interrupts? Who enables bus mastering? The platform driver > that claims the DT node wouldn't know that this is part of a PCI > device, so I guess the PCI driver must do all that stuff? I don't see > it in the xmgmt-drv.c from > https://lore.kernel.org/all/20220305052304.726050-4-lizhi.hou@xilinx.com/ > Yes, the PCI driver will do all that stuff. This xmgmt-drv.c is created
to just populating the devices based on fdt input. It is removed after
the unittest is created which can populate devices and verify the
address translation.
Thanks,
Lizhi
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