Messages in this thread | | | Date | Thu, 29 Jun 2023 08:16:39 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v3] riscv: Discard vector state on syscalls |
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Hey,
On Thu, Jun 29, 2023 at 08:27:30AM +0200, Björn Töpel wrote: > From: Björn Töpel <bjorn@rivosinc.com> > > The RISC-V vector specification states: > Executing a system call causes all caller-saved vector registers > (v0-v31, vl, vtype) and vstart to become unspecified. > > The vector registers are set to all 1s, vill is set (invalid), and the > vector status is set to Dirty. > > That way we can prevent userspace from accidentally relying on the > stated save. > > Rémi pointed out [1] that writing to the registers might be > superfluous, and setting vill is sufficient. > > Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] > Suggested-by: Darius Rad <darius@bluespec.com> > Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> > Suggested-by: Rémi Denis-Courmont <remi@remlab.net> > Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
clang allmodconfig and rv32_defconfig fail to build with this patch, according to patchwork: ../arch/riscv/kernel/traps.c:299:3: error: call to undeclared function 'riscv_v_vstate_discard'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
Cheers, Conor.
> --- > > v2->v3: > Set state to Dirty after discard, for proper ptrace() handling > (Andy) > > v1->v2: > Proper register restore for initial state (Andy) > Set registers to 1s, and not 0s (Darius) > > --- > arch/riscv/include/asm/vector.h | 33 +++++++++++++++++++++++++++++++++ > arch/riscv/kernel/traps.c | 2 ++ > 2 files changed, 35 insertions(+) > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > index 04c0b07bf6cd..0b23056503c5 100644 > --- a/arch/riscv/include/asm/vector.h > +++ b/arch/riscv/include/asm/vector.h > @@ -33,6 +33,11 @@ static inline void __riscv_v_vstate_clean(struct pt_regs *regs) > regs->status = (regs->status & ~SR_VS) | SR_VS_CLEAN; > } > > +static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) > +{ > + regs->status = (regs->status & ~SR_VS) | SR_VS_DIRTY; > +} > + > static inline void riscv_v_vstate_off(struct pt_regs *regs) > { > regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; > @@ -128,6 +133,34 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ > riscv_v_disable(); > } > > +static inline void __riscv_v_vstate_discard(void) > +{ > + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); > + > + riscv_v_enable(); > + asm volatile ( > + ".option push\n\t" > + ".option arch, +v\n\t" > + "vsetvli %0, x0, e8, m8, ta, ma\n\t" > + "vmv.v.i v0, -1\n\t" > + "vmv.v.i v8, -1\n\t" > + "vmv.v.i v16, -1\n\t" > + "vmv.v.i v24, -1\n\t" > + "vsetvl %0, x0, %1\n\t" > + ".option pop\n\t" > + : "=&r" (vl) : "r" (vtype_inval) : "memory"); > + riscv_v_disable(); > +} > + > +static inline void riscv_v_vstate_discard(struct pt_regs *regs) > +{ > + if ((regs->status & SR_VS) == SR_VS_OFF) > + return; > + > + __riscv_v_vstate_discard(); > + __riscv_v_vstate_dirty(regs); > +} > + > static inline void riscv_v_vstate_save(struct task_struct *task, > struct pt_regs *regs) > { > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c > index 5158961ea977..5ff63a784a6d 100644 > --- a/arch/riscv/kernel/traps.c > +++ b/arch/riscv/kernel/traps.c > @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) > regs->epc += 4; > regs->orig_a0 = regs->a0; > > + riscv_v_vstate_discard(regs); > + > syscall = syscall_enter_from_user_mode(regs, syscall); > > if (syscall < NR_syscalls) > > base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 > -- > 2.39.2 > [unhandled content-type:application/pgp-signature] | |