Messages in this thread | | | Date | Fri, 23 Jun 2023 21:47:12 +0800 | From | kernel test robot <> | Subject | Re: [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable |
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Hi Heiko,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20230622] [cannot apply to linus/master v6.4-rc7 v6.4-rc6 v6.4-rc5 v6.4-rc7] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Heiko-Stuebner/RISC-V-move-vector-available-status-into-a-dedicated-variable/20230623-081314 base: next-20230622 patch link: https://lore.kernel.org/r/20230622231305.631331-3-heiko%40sntech.de patch subject: [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20230623/202306232112.kwDtMcou-lkp@intel.com/config) compiler: riscv64-linux-gcc (GCC) 12.3.0 reproduce: (https://download.01.org/0day-ci/archive/20230623/202306232112.kwDtMcou-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202306232112.kwDtMcou-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/riscv/kernel/setup.c: In function 'setup_arch': >> arch/riscv/kernel/setup.c:315:17: error: implicit declaration of function 'riscv_vector_supported'; did you mean 'riscv_noncoherent_supported'? [-Werror=implicit-function-declaration] 315 | riscv_vector_supported(); | ^~~~~~~~~~~~~~~~~~~~~~ | riscv_noncoherent_supported cc1: some warnings being treated as errors
vim +315 arch/riscv/kernel/setup.c
304 305 if (!acpi_disabled) 306 acpi_init_rintc_map(); 307 308 riscv_init_cbo_blocksizes(); 309 riscv_fill_hwcap(); 310 init_rt_signal_env(); 311 apply_boot_alternatives(); 312 313 if (IS_ENABLED(CONFIG_RISCV_ISA_V) && 314 riscv_isa_extension_available(NULL, v)) > 315 riscv_vector_supported(); 316 317 if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && 318 riscv_isa_extension_available(NULL, ZICBOM)) 319 riscv_noncoherent_supported(); 320 } 321
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