Messages in this thread | | | Date | Thu, 22 Jun 2023 14:58:37 -0400 | From | "Stefan O'Rear" <> | Subject | Re: [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling |
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On Thu, Jun 22, 2023, at 1:39 PM, Heiko Stübner wrote: > Am Dienstag, 13. Juni 2023, 08:35:53 CEST schrieb Stefan O'Rear: >> vxrm and vxsat are part of fcsr in 0.7.1, so they should already have been >> handled by __fstate_save and __fstate_restore, and this code is likely to >> misbehave (saving the new process's vxrm/vxsat in the old process's save area >> because float state is swapped before vector state in __switch_to). > > I'm not sure I follow your description but may be overlooking or have > misunderstood something. > > Somehow I way to often have trouble resolving CSR addresses, but according > to openSBI, FCSR has the location of 0x3 > (#define CSR_FCSR 0x003 in include/sbi/riscv_encoding.h) > > where CSR_VXSAT and CSR_VXRM are at 0x9 and 0xa respectively. > (#define CSR_VXSAT 0x9 and #define CSR_VXRM 0xa) > > > And looking at __fstate_save + __fstate_restore the only CSRs accessed seem > to be CSR_STATUS and FCSR itself. > > I definitly won't claim to be right, but don't see the issue yet. > > > Thanks for a hint > Heiko
Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in riscv-v-spec-0.7.1.pdf?
-s
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