Messages in this thread | | | From | "Kubalewski, Arkadiusz" <> | Subject | RE: [RFC PATCH v8 08/10] ice: implement dpll interface to control cgu | Date | Mon, 19 Jun 2023 20:34:12 +0000 |
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>From: Jiri Pirko <jiri@resnulli.us> >Sent: Saturday, June 10, 2023 6:37 PM > >Fri, Jun 09, 2023 at 02:18:51PM CEST, arkadiusz.kubalewski@intel.com wrote: > >[...] > > >>+static int ice_dpll_mode_get(const struct dpll_device *dpll, void *priv, >>+ enum dpll_mode *mode, >>+ struct netlink_ext_ack *extack) >>+{ >>+ *mode = DPLL_MODE_AUTOMATIC; > >I don't understand how the automatic mode could work with SyncE. The >There is one pin exposed for one netdev. The SyncE daemon should select >exacly one pin. How do you achieve that? >Is is by setting DPLL_PIN_STATE_SELECTABLE on the pin-netdev you want to >select and DPLL_PIN_STATE_DISCONNECTED on the rest? > > >[...]
AUTOMATIC mode autoselects highest priority valid signal. As you have pointed out, for SyncE selection, the user must be able to manually select a pin state to enable recovery of signal from particular port.
In "ice" case there are 2 pins for network PHY clock signal recovery, and both are parent pins (MUX-type). There are also 4 pins assigned to netdevs (one per port). Thus passing a signal from PHY to the pin is done through the MUX-pin, by selecting proper state on pin-parent pair (where parent pins is highest prio pin on dpll).
Thank you! Arkadiusz
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