Messages in this thread | | | Date | Tue, 9 May 2023 14:44:37 +0530 | Subject | Re: [PATCH 4/4] clk: qcom: Add GCC driver support for SDX75 | From | Taniya Das <> |
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Thanks Dmitry for the review.
On 4/20/2023 3:40 PM, Dmitry Baryshkov wrote: >> +static const struct clk_parent_data gcc_parent_data_5[] = { >> + { .fw_name = "emac0_sgmiiphy_rclk" }, > > So, this looks like a mixture of fw_name and index clocks. Please > migrate all of fw_names to the .index usage. >
I will take care of it to move to index, but does it not bind us to use the right index always from DT.
The current approach I was thinking to bind the XO clock to 0th index, but we cannot gurantee these external clocks would be placed at the right index.
>> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_6[] = { >> + { P_EMAC0_SGMIIPHY_TCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_6[] = { >> + { .fw_name = "emac0_sgmiiphy_tclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_7[] = { >> + { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_7[] = { >> + { .fw_name = "emac0_sgmiiphy_mac_rclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_8[] = { >> + { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_8[] = { >> + { .fw_name = "emac0_sgmiiphy_mac_tclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_9[] = { >> + { P_EMAC1_SGMIIPHY_RCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_9[] = { >> + { .fw_name = "emac1_sgmiiphy_rclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_10[] = { >> + { P_EMAC1_SGMIIPHY_TCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_10[] = { >> + { .fw_name = "emac1_sgmiiphy_tclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_11[] = { >> + { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_11[] = { >> + { .fw_name = "emac1_sgmiiphy_mac_rclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_12[] = { >> + { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_12[] = { >> + { .fw_name = "emac1_sgmiiphy_mac_tclk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_13[] = { >> + { P_PCIE_1_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_13[] = { >> + { .fw_name = "pcie_1_pipe_clk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_14[] = { >> + { P_PCIE_2_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_14[] = { >> + { .fw_name = "pcie_2_pipe_clk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_15[] = { >> + { P_PCIE20_PHY_AUX_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_15[] = { >> + { .fw_name = "pcie20_phy_aux_clk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_16[] = { >> + { P_PCIE_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_16[] = { >> + { .fw_name = "pcie_pipe_clk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_17[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GPLL0_OUT_MAIN, 1 }, >> + { P_GPLL6_OUT_MAIN, 2 }, >> + { P_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_17[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gpll0.clkr.hw }, >> + { .hw = &gpll6.clkr.hw }, >> + { .hw = &gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_18[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GPLL0_OUT_MAIN, 1 }, >> + { P_GPLL8_OUT_MAIN, 2 }, >> + { P_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_18[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gpll0.clkr.hw }, >> + { .hw = &gpll8.clkr.hw }, >> + { .hw = &gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_19[] = { >> + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_19[] = { >> + { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = { >> + .reg = 0x71060, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_5, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac0_cc_sgmiiphy_rx_clk_src", >> + .parent_data = gcc_parent_data_5, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_5), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = { >> + .reg = 0x71058, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_6, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac0_cc_sgmiiphy_tx_clk_src", >> + .parent_data = gcc_parent_data_6, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_6), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = { >> + .reg = 0x71098, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_7, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac0_sgmiiphy_mac_rclk_src", >> + .parent_data = gcc_parent_data_7, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_7), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = { >> + .reg = 0x71094, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_8, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac0_sgmiiphy_mac_tclk_src", >> + .parent_data = gcc_parent_data_8, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_8), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = { >> + .reg = 0x72060, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_9, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac1_cc_sgmiiphy_rx_clk_src", >> + .parent_data = gcc_parent_data_9, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_9), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = { >> + .reg = 0x72058, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_10, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac1_cc_sgmiiphy_tx_clk_src", >> + .parent_data = gcc_parent_data_10, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_10), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = { >> + .reg = 0x72098, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_11, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac1_sgmiiphy_mac_rclk_src", >> + .parent_data = gcc_parent_data_11, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_11), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = { >> + .reg = 0x72094, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_12, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_emac1_sgmiiphy_mac_tclk_src", >> + .parent_data = gcc_parent_data_12, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_12), >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { >> + .reg = 0x67084, >> + .shift = 0, >> + .width = 2, >> + .parent_map = gcc_parent_map_13, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_1_pipe_clk_src", >> + .parent_data = gcc_parent_data_13, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_13), >> + .ops = &clk_regmap_mux_closest_ops, > > Are these clocks a clk_regmap_mux_closest_ops in reality > clk_regmap_phy_mux_ops?
clk_regmap_phy_mux_ops cannot be used here, as multi parent mux requires the .get_parent ops to be supported.
> >> + }, >> + },
-- Thanks & Regards, Taniya Das.
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