Messages in this thread | | | Date | Mon, 8 May 2023 14:57:52 +0530 | From | Vinod Koul <> | Subject | Re: [PATCH v3 1/5] phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit |
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On 26-04-23, 13:29, Dmitry Rokosov wrote: > Previously, all Amlogic boards used the XTAL clock as the default board > clock for the USB PHY input, so there was no need to enable it. > However, with the introduction of new Amlogic SoCs like the A1 family, > the USB PHY now uses a gated clock. Hence, it is necessary to enable > this gated clock during the PHY initialization sequence, or disable it > during the PHY exit, as appropriate.
Applied to phy/next, thanks
-- ~Vinod
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