Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | Date | Fri, 5 May 2023 19:54:44 +0200 | From | Simon Horman <> | Subject | Re: [PATCH v6 09/14] x86: Secure Launch SMP bringup support |
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On Thu, May 04, 2023 at 02:50:18PM +0000, Ross Philipson wrote: > On Intel, the APs are left in a well documented state after TXT performs > the late launch. Specifically they cannot have #INIT asserted on them so > a standard startup via INIT/SIPI/SIPI cannot be performed. Instead the > early SL stub code parked the APs in a pause/jmp loop waiting for an NMI. > The modified SMP boot code is called for the Secure Launch case. The > jump address for the RM piggy entry point is fixed up in the jump where > the APs are waiting and an NMI IPI is sent to the AP. The AP vectors to > the Secure Launch entry point in the RM piggy which mimics what the real > mode code would do then jumps to the standard RM piggy protected mode > entry point. > > Signed-off-by: Ross Philipson <ross.philipson@oracle.com>
Hi Ross,
just one minor nit on this one.
> /* > * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad > * (ie clustered apic addressing mode), this is a LOGICAL apic ID. > @@ -1132,6 +1210,13 @@ static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, > cpumask_clear_cpu(cpu, cpu_initialized_mask); > smp_mb(); > > + /* With Intel TXT, the AP startup is totally different */ > + if ((slaunch_get_flags() & (SL_FLAG_ACTIVE|SL_FLAG_ARCH_TXT)) ==
nit: spaces around '|'
> + (SL_FLAG_ACTIVE|SL_FLAG_ARCH_TXT)) { > + boot_error = slaunch_wakeup_cpu_from_txt(cpu, apicid); > + goto txt_wake; > + }
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