Messages in this thread | | | From | Christian Gmeiner <> | Date | Tue, 30 May 2023 10:21:17 +0200 | Subject | Re: [PATCH v2 0/3] Cadence PCIe PHY latency for PTM |
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Hi Dominic
Am Do., 27. Apr. 2023 um 07:50 Uhr schrieb Dominic Rath <rath@ibv-augsburg.de>: > > Hello Everyone, > > this series adds PHY latency properties to the Cadence PCIe > driver to improve PTM accuracy, and configures the necessary > values for TI's AM64x processors. > > These latencies are implementation specific and need to be > configured in the PCIe IP core's registers to allow the > PCIe controller to exactly determine the RX/TX timestamps for > PCIe PTM messages. > > TI doesn't document these values in the datasheet or reference > manual as of now, but provided the necessary data via TI's E2E > forums (see PATCH 3/3). > > Changes from v1 to v2: > - move latency property to PHY instead of PCIe controller > - drop vendor prefix from property name > - rephrase commit message regarding optional properties > - emit an info message instead of a warning in case > an optional property is missing > > Best Regards, >
Hope you send out a v3 soon.
-- greets -- Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
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