Messages in this thread | | | Date | Sun, 21 May 2023 23:57:55 +0300 | Subject | Re: [PATCH V2 1/2] dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings | From | Dmitry Baryshkov <> |
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On 19/05/2023 11:57, Devi Priya wrote: > Add bindings for the PCIe QMP PHYs found on IPQ9574. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V2: > - Picked up the R-b tag > - Did not convert the clock IDs to numerical values as the clock > header (dependent patch) is merged in latest rc1. > > .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml > new file mode 100644 > index 000000000000..7c8012647051 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QMP PHY controller (PCIe, IPQ9574) > + > +maintainers: > + - Vinod Koul <vkoul@kernel.org> > + > +description: > + The QMP PHY controller supports physical layer functionality for a number of > + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. > + > +properties: > + compatible: > + enum: > + - qcom,ipq9574-qmp-gen3x1-pcie-phy > + - qcom,ipq9574-qmp-gen3x2-pcie-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 5 > + > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: anoc_lane > + - const: snoc_lane > + - const: pipe
Could you please reorder the clocks in the following way: - aux - cfg_ahb - pipe - .. the rest
This will allow us to use this schema for other IPQ QMP PCIe PHYs.
> + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: phy > + - const: common > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + - "#clock-cells" > + - clock-output-names > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> > + #include <dt-bindings/reset/qcom,ipq9574-gcc.h> > + > + pcie0_phy: phy@84000 { > + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > + reg = <0x00084000 0x1000>; > + > + clocks = <&gcc GCC_PCIE0_AUX_CLK>, > + <&gcc GCC_PCIE0_AHB_CLK>, > + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>, > + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>, > + <&gcc GCC_PCIE0_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe"; > + > + resets = <&gcc GCC_PCIE0_PHY_BCR>, > + <&gcc GCC_PCIE0PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie0_pipe_clk_src"; > + > + #phy-cells = <0>; > + };
-- With best wishes Dmitry
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