Messages in this thread | | | Subject | Re: [PATCH 1/3] MIPS: Introduce WAR_4KC_LLSC config option | From | Jiaxun Yang <> | Date | Fri, 19 May 2023 22:51:04 +0100 |
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> 2023年5月19日 21:23,Maciej W. Rozycki <macro@orcam.me.uk> 写道: > > On Fri, 19 May 2023, Jiaxun Yang wrote: > >> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c >> index 6d15a398d389..fd452e68cd90 100644 >> --- a/arch/mips/kernel/cpu-probe.c >> +++ b/arch/mips/kernel/cpu-probe.c >> @@ -152,6 +152,13 @@ static inline void check_errata(void) >> struct cpuinfo_mips *c = ¤t_cpu_data; >> >> switch (current_cpu_type()) { >> + case CPU_4KC: >> + if ((c->processor_id & PRID_REV_MASK) < PRID_REV_4KC_V1_0) { >> + c->options &= ~MIPS_CPU_LLSC; >> + if (!IS_ENABLED(CONFIG_WAR_4K_LLSC)) >> + pr_err("CPU have LLSC errata, please enable CONFIG_WAR_4K_LLSC"); > > Given the circumstances I think this should be `panic'. You don't want > to continue with a system that can randomly lock up.
I just checked how other architectures handle such situation, it seems like TAINT_CPU_OUT_OF_SPEC is a better option.
Panic in cpu_probe can be frustrating for users as it is earlier than initialisation of consoles so the panic message can never be read by users.
> > Also "CPU has LLSC erratum, [...]" as both are singular.
Thanks for the tip :-) - Jiaxun
> > Maciej
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