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    Subject[PATCH v4 07/10] riscv: dts: bouffalolab: add the bl808 SoC base device tree
    Date
    Add a baisc dtsi for the bouffalolab bl808 SoC.

    Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
    Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
    ---
    arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 73 ++++++++++++++++++++++
    1 file changed, 73 insertions(+)
    create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi

    diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
    new file mode 100644
    index 000000000000..87906fe51db5
    --- /dev/null
    +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
    @@ -0,0 +1,73 @@
    +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
    +/*
    + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
    + */
    +
    +#include <dt-bindings/interrupt-controller/irq.h>
    +
    +/ {
    + compatible = "bouffalolab,bl808";
    + #address-cells = <1>;
    + #size-cells = <1>;
    +
    + cpus {
    + timebase-frequency = <1000000>;
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + compatible = "thead,c906", "riscv";
    + device_type = "cpu";
    + reg = <0>;
    + d-cache-block-size = <64>;
    + d-cache-sets = <256>;
    + d-cache-size = <32768>;
    + i-cache-block-size = <64>;
    + i-cache-sets = <128>;
    + i-cache-size = <32768>;
    + mmu-type = "riscv,sv39";
    + riscv,isa = "rv64imafdc";
    +
    + cpu0_intc: interrupt-controller {
    + compatible = "riscv,cpu-intc";
    + interrupt-controller;
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + };
    + };
    + };
    +
    + xtal: xtal-clk {
    + compatible = "fixed-clock";
    + #clock-cells = <0>;
    + /* This value must be overridden by the board */
    + clock-frequency = <0>;
    + };
    +
    + soc {
    + compatible = "simple-bus";
    + ranges;
    + interrupt-parent = <&plic>;
    + dma-noncoherent;
    + #address-cells = <1>;
    + #size-cells = <1>;
    +
    + uart3: serial@30002000 {
    + compatible = "bouffalolab,bl808-uart";
    + reg = <0x30002000 0x1000>;
    + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&xtal>;
    + status = "disabled";
    + };
    +
    + plic: interrupt-controller@e0000000 {
    + compatible = "bouffalolab,bl808-plic", "thead,c900-plic";
    + reg = <0xe0000000 0x4000000>;
    + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
    + interrupt-controller;
    + #address-cells = <0>;
    + #interrupt-cells = <2>;
    + riscv,ndev = <82>;
    + };
    + };
    +};
    --
    2.40.0
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